View W81282F_955057.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W81282F
USB Keyboard Controller with 4 Ports Hub
W81282F Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 10 n.a. Dates 08/27/99 Version 0.50 Version on Web n.a. First published. Main Contents
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W81282F
Preliminary
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. GENERAL DESCRIPTION .................................................................................................................1 APPLICATION BLOCK DIAGRAM ....................................................................................................1 FEATURES ............................................................................................................................................2 PIN CONFIGURATION .......................................................................................................................3 PIN DESCRIPTION .............................................................................................................................4 ABSOLUTE MAXIMUM RATINGS ....................................................................................................8 ELECTRICAL CHARACTERISTICS..................................................................................................9 TYPICAL APPLICATION .................................................................................................................. 11 HOW TO READ THE TOP MARKING............................................................................................. 13 PACKAGE DIMENSIONS ............................................................................................................... 14
Publication Release Date: Aug. 1999 -1Revision 0.5
W81282F
USB HUB CONTROLLER 1. GENERAL DESCRIPTION
The W81282F is a highly integrated USB keyboard with 4 port hub controller chip. The W81282F has a built-in 21X8 default keyboard matrix, so that it can be directly connected to keyboard with multi-media function matrix. The keyboard matrix, vendor ID, and device ID can be easily customized from an optional EEPROM or modify firmware to meet any customers' requirement. The 4 USB down-stream port can be used to connect various USB peripheral devices, such as printer, modem, speaker, camera, mice, and joystick, to system without any external glue logics. The W81282F use 12MHz clock input with internal PLL to eliminate EMI effect. The W81282F also built-in ESD/EFT protection circuit so it can pass ESD/EFT test without any external glue logics.
2.
APPLICATION BLOCK DIAGRAM
4 PORT USB DOWNLINK
(Optional) ID, Matrix Loadable
HOST
EEPROM
KB MATRIX
W81282F
Volume Control
Publication Release Date: Aug. 1999 -1Revision 0.71
W81282F
PRELIMINARY 3. FEATURES
* Full compliance with USB spec Rev 1.1 and HID Class Definition Rev 1.0 * Embedded microprocessor--8052 ( 6K ROM + 256 Byte RAM) * Support auto-detected two power source mode between bus power mode and self power mode. * 12-Mhz crystal/oscillator input to lower EMI * Support Suspend and Resume operation * Support ACPI features * Four downstream ports with per port over-current protection * Single 5V supplied with embedded 5V-3.3V regulator * Provides the external pull-up resistor control for the up-stream connection. * Per-port/Global power control optional * Built-in ESD/EFT protection circuit * Support 21 X 8 keyboard matrix * Support consumer control function for multi-media * Support optional EEPROM for vendor ID, device ID, and KB matrix down load * Support encoder input for audio volume control * Provide the external pull-up resistor control for the up-stream connect * 100-pin PQFP * 5V CMOS device
Publication Release Date: Aug. 1999 -2Revision 0.5
W81282F
PRELIMINARY 4. PIN CONFIGURATION
GND3V GND3V SO13(P25) SO12(P24)) EECLK/IDSEL0(P30) SO11(P23) FWKP5# SO10(P22) UPWEN1# SO09(P21) OVRI1# SO08(P20) N.C. GND GND SO19 SO20(P34) UPWEN2# P35 XWR#(P36) OVRI2#
DP4 DM4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
8 7 7 7 7 7 7 7 7 7 7 6 66 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 0 9 8 7 6 5 4 3 2 1 0 9 87 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 OVRI4# SO03(P04) SO18 SO02(P05) SO01(P06) VDD SO00(P07) N .C. XTAL2 XTAL1 GND N .C. N .C. LEDEN1# PLLE LEDEN2# RB LEDEN3#
N.C. N.C.
DP3 DM3
N.C.
GND3V GND3V DP2 DM2
W81282F
N.C. N.C.
DP1 DM1 GND3V GND3V
N.C.
DP0 DM0
SO07(P00) LEDEN0# SO06(P01) UPWEN3# SO05(P02) OVRI3# UPWEN4# SO04(P03)
XRD#(P37)
RA LEDEN4#
111111 111122222222223 1 234 56 78 9012345 67 8901234 567890
VDD3V VDDA SO14 (P26) GNDA VBUS SO15(P27) LED0# SI0(P10) LED1# SI11(P11) LED2# SI2(P12) LEDOVR# SI3(P13) VDD VDD SI4(P14) N.C. RESET INPUT_P SO16 P33 XINT# (P32) EESDA/IDSEL1(P31) SI5(P15) SI6(P16) SI7(P17) BUSPWR# SO17 GANGED#
Publication Release Date: Aug. 1999 -3Revision 0.5
W81282F
PRELIMINARY 5. PIN DESCRIPTION
Pin Name I/O Type Pin Function Pull Up/ Down 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15,16 17 18 19 20 21 22 23 24 VDD3V VDDA SO14 (P26) GNDA VBUS SO15 (P27) LED0# SI0 (P10) LED1# SI1 (P11) LED2# SI2 (P12) LEDOVR# SI3 (P13) VDD SI4 (P14) N.C. RESET INPUT_P SO16 P33 XINT# (P32) EESDA/IDSEL1 (P31) 25 26 27 SI5 (P15) SI6 (P16) SI7 (P17) IOUD2 IOUD2 IOUD2 Power1 Power1 IOUD2 Power0 IUD2T IOUD2 IOU2P IOUD2 IOU2P IOUD2 IOU2P IOUD2 IOU2P IOUD2 Power1 IOUD2 IOUD2 IUD2T IOUD2 O2 IOUD2 IOUD2 IOUD2
3.3V Regulator Output. Supplying voltage for all transceivers Analog power. Port 2.6 and function of Scan Out line 14. Analog ground. Input of upstream power status. On self-power mode, connection should be controlled by VBUS status. Port 2.7 and function of Scan Out line 15.
Pin Number
U U O U O U O U O U U U U U U U U U U
Keyboard NumLock LED driver. To drive LED directly. Port 1.0 and function of Scan In line 0. Keyboard CapLock LED driver. To drive LED directly. Port 1.1 and function of Scan In line 1. Keboard ScrolLock LED driver. To drive LED directly Port 1.2 and function of Scan In line 2. Flag of any downstream port1 over-current. To drive LED directly Port 1.3 and function of Scan In line 3. Digital supply voltage. Port 1.4 and function of Scan In line 4. No connection. This pin should be floated. Master reset input. Active high. A programmable port and reverse for input application. This pin is function of Scan Out line 16. Port 3.3 and reverse for input or output application. Port 3.2. This pin is dedicated for internal use. Port 3.1 and function of serial data line interfacing with external EEPROM. If no serial EEPROM present, this pin is used to scan ID selection and named IDSEL1 Port 1.5 and function of Scan In line 5. Port 1.6 and function of Scan In line 6. Port 1.7 and function of Scan In line 7.
Publication Release Date: Aug. 1999 -4Revision 0.5
W81282F
PRELIMINARY
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 BUSPWR# SO17 GANGED# LEDEN4# RA LEDEN3# RB LEDEN2# PLLE LEDEN1# N.C. N.C. GND XTAL1 XTAL2 N.C. SO00 (P07) VDD SO01 (P06) SO02 (P05) SO18 SO03 (P04) OVRI4# SO04 (P03) UPWEN4# OVRI3# SO05 (P02) UPWEN3# SO06 (P01) LEDEN0# SO07 (P00) IUD2 IOU2P IUD2 IOU2P IUD2 IOU2P IUD2 IOU2P IUD2 IOU2P IUD2 IUD2 Power0 OSCM OSCM IUD2 IOUD2 Power1 IOUD2 IOUD2 O2 IOUD2 IUD2T IOUD2 O2 IUD2T IOUD2 O2 IOUD2 IOU2P IOUD2
Buspower/Selfpower control setting. This pin should be floated or tied to VDD. This pin is function of Scan Out line 17. Ganged/Individual downstream power switch control setting. Default is Individual mode. Downstream port4 LED. Active low when port4 enable. This pin is a Rotation A input for consumer HID application. Downstream port3 LED. Active low when port3 enable. This pin is a Rotation B input for consumer HID application. Downstream port2 LED. Active low when port2 enable. PLL clock generator enable/disable control. It should be tied to VDD. (PLLE=1, clock=12MHz ; PLLE=0,clock=48MHz) Downstream port1 LED. Active low when port1 enable. No connection. This pin should be floated. No connection. This pin should be floated. Digital ground Clock In. (12MHz Clock Out. No connection. This pin should be floated. Port 0.7 and function of Scan Out line 0. Digital supply voltage. Port 0.6 and function of Scan Out line 1. Port 0.5 and function of Scan Out line 2. This pin is function of Scan Out line 18. Port 0.4 and function of Scan Out line 3. Downstream port4 over-current status input. Active low. Port 0.3 and function of Scan Out line 4. Downstream port4 power control. Active low. Downstream port3 over-current status input. Active low. Port 0.2 and function of Scan Out line 5. Downstream port3 power control. Active low. Port 0.1 and function of Scan Out line 6. Up_stream port LED. Active low when up_stream port enable. Port 0.0 and function of Scan Out line 7. when PLLE=1, 48MHz when PLLE=0)
D O U O U O U O U O U U D U U U U U U U O U
Publication Release Date: Aug. 1999 -5Revision 0.5
W81282F
PRELIMINARY
59 60 61 62 63 64 65 66,67 68 69 70 71 72 73 74 75 76 77 78 79,80 81 82 83,84 85 86 87 88,89 90 91 XRD# (P37) OVRI2# XWR# (P36) P35 UPWEN2# SO20 (P34) SO19 GND N.C. SO08 (P20) OVRI1# SO09 (P21) UPWEN1# SO10 (P22) FWKP5# SO11 (P23) EECLK/IDSEL0 (P30) SO12 (P24) SO13 (P25) GND3V DP4 DM4 N.C. DP3 DM3 N.C. GND3V DP2 DM2 IOUD2 IOUD2 Power0 AIO AIO AIO AIO Power0 AIO AIO IOUD2 IUD2T IOUD2 IOUD2 O2 IOUD2 O2 Power0 IOUD2 IOUD2 IUD2T IOUD2 O2 IOUD2 IUD2 IOUD2 IOUD2
Port 3.7.This pin is dedicated for internal use.
U U U U U U U U D U U U U -
Downstream port2 over-current status input. Active low. Port 3.6.This pin is dedicated for internal use.
Port 3.5 and reverse for input or output application. Downstream port2 power control. Active low. Port 3.4 and function of Scan Out line 20. This pin is function of Scan Out line 19. Digital ground. No connection. This pin should be floated. Port 2.0 and function of Scan Out line 8.
Downstream port1 over-current status input. Active low. Port 2.1 and function of Scan Out line 9. Downstream port1 power control. Active low. Port 2.2 and function of Scan Out line 10. Embedded function wake-up input. Can be used for Wake-up hot key. Port 2.3 and function of Scan Out line 11. This pin is Port 3.0 and function of serial clock line interfacing with external EEPROM. If no serial EEPROM present, this pin is used to scan ID selection and named IDSEL0. Port 2.4 and function of Scan Out line 12. Port 2.5 and function of Scan Out line 13. Ground of port3 and port4 transceivers. USB D+ for downstream port4. USB D- for downstream port4. No connection. USB D+ for downstream port3. USB D- for downstream port3. No connection. Ground of port1 and port2 transceivers. USB D+ for downstream port2. USB D- for downstream port2.
-
-
Publication Release Date: Aug. 1999 -6Revision 0.5
W81282F
PRELIMINARY
92,93 94 95 96,97 98 99 100 N.C. DP1 DM1 GND3V N.C. DP0 DM0 AIO AIO Power0 AIO AIO
No connection. USB D+ for downstream port1. USB D- for downstream port1. Ground of port0 transceivers. No connection. USB D+ for upstream port0. USB D- for upstream port0.
-
-
Publication Release Date: Aug. 1999 -7Revision 0.5
W81282F
PRELIMINARY 6. ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (Vcc to Vss) 5.5V Vss-0.5V to Vcc+0.5V Vss-0.5V to Vcc+0.5V TBD 0 C to 70 C 250 C
o o o
LIMIT
Analog Input Voltage Digital Input Voltage Power Dissipation Ambient Operating Temperature Lead Temperature (Soldering, 10 sec)
Publication Release Date: Aug. 1999 -8Revision 0.5
W81282F
PRELIMINARY 7. ELECTRICAL CHARACTERISTICS
VCC = 5V +/-5%, Ta=0 to 70 C Symbol Icc VOH VOL Io>24ma Io>6ma Ta=70 C Note 8 ILO VDI VSE0 VCM VOLU VCRS CIN Pin to GND 4 -3.5 /-4 Note 3 -2 -3 / -1 -5 0 -15 75 5 15 15 300 Includes VDI range RL of 1.5 k to 3.6 V 2.8 1.3 V< V IN <3.3 V |(D+)-(D-)| -10 0.2 0.8 0.8 2.0 2.5 0.3 3.6 2.0 20 20 3.5 /4 5 44 3 /1 ns ns ns ns V V V pF ns ns ns ns ns ns +10 uA V V
o o o
Operating conditions:
PARAMETER VCC Supply Current Logic Output High Logic Output Low Logic Input Leakage Current USB CHARACTERISTICS Leakage Current: Hi-Z State Output Leakage Input Levels: Differential Input Sensitivity Single Ended Signal "0" Differential Common Mode Range Output Levels: Driver Output Low Driver Output High Output Signal Crossover Voltage Capacitance: Transceiver Capacitance Full Speed Timings: Output Rise/Fall Times Source Differential Driver Jitter to Next Transition / to Paired Transition Differential to EOP transition Skew Hub Differential Data Delay(without cable) Hub Differential Driver Jitter to Next Transition / to Paired Transition (including cable) Data bit width distortion after SOP Hub SE0 Delay Relative to t HDD Hub EOP Output Width Skew Low Speed Timings: Output Rise/Fall Times
Conditions
Min
Max TBD
Unit mA V V uA
2.5
VCC 0.4 10
VOHU RL of 15 k to GND
t R /t F Note 1, 4 (CL= 50 pF) t DJ1 /tDJ2 t DEOP t HDD2 Note 2,3,5 t HDJ1 Note 2,3,5 / t HDJ2 t SOP Note 3,5 t EOPD Note 3,5 t HESK Note 3,5 t R /t F Note 1, 4 (CL= 50 pF) Note 2, 3
Publication Release Date: Aug. 1999 -9Revision 0.5
W81282F
PRELIMINARY
7. ELECTRICAL CHARACTERISTICS, continued
PARAMETER Source Differential Driver Jitter to Next Transition / to Paired Transition Differential to EOP transition Skew Hub Differential Data Delay(without cable) Hub Differential Driver Jitter to Next Transition / to Paired Transition (including cable) Data bit width distortion after SOP Hub SE0 Delay Relative to t HDD Hub EOP Output Width Skew
Symbol t DJ1 /tDJ2 t DEOP
Conditions Note 2, 3 Note 3
Min -25 /-14 -40 -45
Max 25 /14 100 300 45
Unit ns ns ns ns ns
t HDD2 Note 2,3,5 t HDJ1 Note 2,3,5 / HDJ2 t SOP t Note 3,5
/ -45 /-45 -60 0 -300 60 200 300 ns ns ns
t EOPD Note 3,5 t HESK Note 3,5
Note 1: Measured from 10% to 90% of the data signal. Note 2: Timing difference between the differential signals. Note 3: Measured at crossover point of differential data signals. Note 4: The rising and falling edges should be smoothly transiting(monotonic) Note 5: Full Speed timing have a 1.5 k pull-up to 2.8 V on the D+ (DP) data line. Note 6: Low Speed timing have a 1.5 k pull-up to 2.8 V on the D- (DM) data line. Note 7: The maximum load specification is the maximum effective capacitive load allowed that meets the target hub VBUS droop of 330 mV. Note 8: All other USB Electrical Characteristics refer to USB spec Rev 1.1 7.3.2 and 7.3.3.
Publication Release Date: Aug. 1999 - 10 Revision 0.5
W81282F
PRELIMINARY 8. TYPICAL APPLICATION
Publication Release Date: Aug. 1999 - 11 Revision 0.5
W81282F
PRELIMINARY
W81282F Reference Schematic
VCC C2 10u VCC SO15 LEDNUM SI0 LEDCAP SI1 LEDSCR SI2 LEDOVC SI3 SI4 RESET SO16 EESDA SI5 SI6 SI7 SO17 GANGED VOLA VOLB LEDEN2 PLLE LEDEN1 SO14 R9 10K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 + U2 VDD3V VDDA SO14/P26 GNDA VBUS SO15/P27 LED0# SI0/P10 LED1# SI1/P11 LED2# SI2/P12 LEDOVR# SI3/P13 VDD VDD SI4/P14 PSEN# RESET INPUT_P SO16 PSDA/P33 P32/XINT# IDSEL1/EESDA SI5/P15 SI6/P16 SI7/P17 BUSPWR# SO17 GANGED# LEDEN4# VOLUME_A LEDEN3# VOLUME_B LEDEN2# PLLE LEDEN1# XCVREN UC51E GND XTAL1 XTAL2 ROMEN SO00/P07 VDD SO01/P06 SO02/P05 SO18 SO03/P04 OCP4# W81282F-100QFP DD+ NC GND3V GND3V D1D1+ NC NC D2D2+ GND3V GND3V NC D3D3+ NC NC D4D4+ GND3V GND3V SO13/P25 SO12/P24 IDSEL0/EESCL SO11/P23 FWKP5# SO10/P22 PWEN1# SO09/P21 OCP1# SO08/P20 XALE GND GND SO19 SO20/P34 PWEN2# PSCLK/P35 XWR#/P36 OCP2# XRD#/P37 SO07/P00 LEDEN0# SO06/P01 PWEN3# SO05/P02 OCP3# PWEN4# SO04/P03 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C11 15p R15 R16 C10 15p 30 30 CDCD+
R17 R18 C13 15p C12 15p
30 30
CD1CD1+
R19 R20 C15 15p C14 15p
30 30
CD2CD2+
Place R15 ~ R20 & C10 ~ C15 as close as W81282F
VCC
R28 SO13 SO12 EESCL SO11 SO10 PWEN1 SO09 OCP1 SO08
R29
R30
R31
R22 7.5K L6 FB USB1 1 2 3 4 C31 + CT1 10u C16 0.1u 47pF C30 L5 47pF FB UP-PORT 5 6 USB2 USB(A) 1 2 3 4 C27 47pF 5 6 C5 VCC 120u + C26 47pF C7 0.1u C6 PW2 120u + C9 + USB3 USB(A) 1 2 3 4 C29 47pF 5 6 C28 47pF VCC R7 EN0 470 R6 EN1 470 R5 EN2 470 R4 OVC 470 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SO00 SO01 SO02 SO03 SO04 SO05 SO06 SO07 SO08 SO09 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 SO18 SO19 SO20 SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 SO00 SO01 SO02 SO03 SO04 SO05 SO06 SO07 SO08 SO09 SO10 SO11 SO12 SO13 SO14 SO15 SO16 SO17 SO18 SO19 SO20 R1 NUMLK R2 CAPLK R3 SCRLK 470 470 470 0.1u FB(30ohm) R13 15K L3 L4 FB(30ohm) 15K CD2CD2+
15K
15K
15K
15K
CDCD+
SO19 SO20 PWEN2 OCP2 SO07 LEDEN0 SO06 SO05 OCP3 R11 SO04 R12 15K 15K FB(30ohm) L2 CD1CD1+ FB(30ohm) L1 C8 + 0.1u U4 PWEN1 FL1 FL2 PWEN2 1 2 3 4 C/A F/A F/B C/B AIC1526-0 O/A IN GND O/B 8 7 6 5 PW1 R14 Option LEDNUM LEDCAP LEDSCR EESCL D1 D2 D3 LEDEN0 LEDEN1 LEDEN2 LEDOVC D7 LEDNUM LEDCAP D4 D5 D6 LEDSCR VCC R23 R24 R25 R26 10K 10K 10K 10K OCP1 R21 10K R27 10K FL1 FL2 OCP3 OCP4 C18 C17 0.1u 0.1u
X1 X2 SO00 SO01 SO02 SO18 SO03 OCP4
VCC
R32 100K
R33 100K
R34 100K
R35 100K
R36 100K
SO16 SO18 SO19 GANGED PLLE
JP1 JUMPER JP4 JUMPER
JP2 JUMPER JP5 JUMPER
JP3 JUMPER JP6 JUMPER EESDA
VCC
X1 + X2 Y1 12M C4 30p RESET C3 30p R8 8.2K C1 10u
Option
OCP2 VCC U1 1 2 3 4 A0 A1 A2 VSS 24LC04B VCC RC SCL SDA 8 7 6 5 EESCL EESDA
VCC
inbond
Title W81282F Reference Schematic Size Date: Document Number 282DEMO1.SCH Thursday, August 19, 1999 Sheet
WINBOND ELECTRONICS CORP_
Rev 1.0 1 of 1
Publication Release Date: Aug. 1999 - 12 Revision 0.5
W81282F
PRELIMINARY 9. HOW TO READ THE TOP MARKING
Example: The top marking of W81282F-05
inbond
W81282F-05
732AC27242968
1st line: Winbond logo 2nd line: the type number: W81282F-05 3rd line: the tracking code: 732 A C 2 7242968 732: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL ... etc C: IC revision; B means version B, C means version C 2: wafers manufactured in Winbond FAB 2 7242968: wafer production series lot number
Publication Release Date: Aug. 1999 - 13 Revision 0.5
W81282F
PRELIMINARY 10. PACKAGE DIMENSIONS
(100-pin QFP)
HD D
100 81
Dimension in inches
Dimension in mm
Symbol
1 80
Min. Nom. Max.
0.130 0.004 0.107 0.010 0.004 0.546 0.782 0.020 0.728 0.964 0.039 0.087 0.112 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.094 0.117 0.016 0.010 0.556 0.792 0.032 0.752 0.988 0.055 0.103 0.004 0 12
Min. Nom. Max.
3.30 0.10 2.73 0.25 0.10 13.87 19.87 0.50 18.49 24.49 1.00 2.21 2.85 0.30 0.15 14.00 20.00 0.65 18.80 24.80 1.20 2.40 2.97 0.40 0.25 14.13 20.13 0.80 19.10 25.10 1.40 2.62 0.10 0 12
E HE
A A1 A2 b c D E e HD HE L L1 y
q
Notes:
30
51
31
e
b
50
c A2 A1 y A
q
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Seating Plane
See Detail F
L L1 Detail F
Publication Release Date: Aug. 1999 - 14 Revision 0.5
W81282F
PRELIMINARY
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Publication Release Date: Aug. 1999 - 15 Revision 0.5

▲Up To Search▲

Price & Availability of W81282F

	To Download W81282F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .